Field of the Invention
The present invention relates generally to semiconductor packaging, and more specifically, to a semiconductor package having blind vias for interconnecting a metal layer atop the semiconductor package to internal circuits of the semiconductor package.
Description of the Related Art
Semiconductor packages that provide mechanical mounting and electrical interconnection of a semiconductor die are commonly provided in ball grid array and land grid array configurations. A semiconductor die is electrically connected to a substrate with a grid array terminals disposed on the “bottom” side of the semiconductor package and solder balls are attached for connection to a system substrate, typically a printed circuit board (PCB) having lands located to attach the solder balls of the semiconductor package (referred to as ball grid array or BGA attach). Alternatively, conductive paste, a socket or “interposer” may be used to provide contacts between lands of the semiconductor package and lands on the system substrate (referred to as land grid array or LGA connection).
The above-incorporated Parent U.S. Patent Application discloses a top-surface mounting terminal structure for attaching a second semiconductor package or die to the top of a first semiconductor package. While the packaging density of the combined devices is increased, the location of the terminals is dictated by the design of the die or semiconductor package mounted on the first semiconductor package, which typically increases the interconnect density of the substrate in the first semiconductor package.
Also, it is often desirable to provide a metal shield cap atop a semiconductor package. Such shields are usually connected to a ground terminal or other reference voltage level by a through via extending through the semiconductor package to one or more terminals.
Therefore, it would be desirable to improve upon the techniques of the above-incorporated parent U.S. Patent Application to provide a semiconductor package and a method of manufacturing such a semiconductor package that facilitates stacking of grid arrays and other components while reducing interconnect densities in the semiconductor package and increases flexibility of design. It would further be desirable to improve the techniques of the above-incorporated parent U.S. Patent Application to provide a semiconductor package and method of manufacture that provides a metal shield cap without requiring additional through vias.